This invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device, such as, a flash memory.
First, description will be made about a related semiconductor memory device with reference to FIG. 1.
As illustrated in FIG. 1, a related semiconductor memory device, such as, a flash memory or an EEPROM (Electrically Erasable Programmable ROM), includes a plurality of memory cells MC1-MCn, row sub-decoders (namely, word line driving circuits) SD, and a plurality of row main decoders MD. Herein, it is to be noted that only one decoder MD is illustrated in FIG. 1 for convenience.
In this event, each memory cell MC1-MCn is electrically writable and erasable, and each row sub-decoder SD selects a row of each memory cell MC1-MCn. Further, each row main decoder MD decodes a row address signal and supplies output signals XB, XB to the row sub-decodes SD.
In this case, the row main decoder is composed of two stages of level shift circuits 15, 16 and the output signals XB and XB thereof are complementary to each other.
Herein, a memory cell array is structured by a plurality of memory cells arranged in a matrix form. With such a structure, a plurality of word lines WL are connected to control gates of the respective memory cells arranged in the row direction while a plurality of bit lines BL are connected to drains of the respective memory cells arranged in the row direction. In this event, a plurality of word lines WL are divided into some blocks, and each block is selected by one of the row main decoders MD.
The row sub-decoder SD for selecting the row of the memory cell MC1 is composed of one p-channel transistor P11 and two of n-channel transistors N11, N12. In this case, sources of the transistor P11 and the transistor N11 are connected to an XSPP node which is given a pre-decode signal (XSPP) while a source of the transistor N12 is coupled to a ground terminal (GND).
Drains of the respective transistors P11, N11, N12 are connected to the word line (WL). Further, the output signal XB is given to gates of the transistor P11 and the transistor N12 while the output signal XB is given to a gate of the transistor N11.
Moreover, a back gate of the transistor P11 is coupled to a back gate voltage (PBG) node while back gates of the both transistors N11, N12 are connected to a back gate voltage (NBG) node, respectively.
Each of the row sub-decoders for driving the other memory cells MC2-MCn is structured by the respective transistors Pn1, Nn1, Nn2 in the same manner. These row sub-decoders are controlled by the pre-decode signals XSPP and the output signals XB, XB to determine potential of each word line (WN).
As will be described later, potential difference between the drain of each transistor P11, N11, N12 and the back gate often becomes high during a writing operation or an erasing operation. In this case, when a threshold value Vt of each transistor is lowered, leak current often flows because of sub-threshold or punch-through phenomenon. To prevent this, the back gate voltage of each transistor P11, N1, N12 is switched in accordance with an operation mode.
A first level shift circuit 15 is composed of two pairs of transistors which are connected between a mode switching power supply (VPX) node and a ground node in series. More specifically, the level shift circuit 15 is composed of a p-channel transistor PM1 and an n-channel transistor NM1, and a p-channel transistor PN2 and an n-channel transistor NM2.
With such a structure, an output of a NAND gate 13 is given to a gate of the transistor NM1 while an output of an inverter circuit 14 is given to a gate of the transistor NM2. Further, a series connection point between the transistor PM1 and the transistor NM1 is coupled to a gate of the transistor PM2 while a series connection point between the transistor PM2 and the transistor NM2 is coupled to a gate of the transistor PM1.
Subsequently, description will be made about an operation of the first level shift circuit 15.
When an output of the NAND gate 13 is equal to 0V, an output of the inverter 14 becomes VDD to turn on the transistor NM2. Thereby, the drain of the transistor NM2 and the gate of the transistor PM1 are put into 0V, respectively.
In consequence, the transistor PM1 is turned on, and the drain of the transistor PM1 and the gate of the transistor PM2 are put into VPX. At this time, the transistors NM1 and PM2 are turned off.
Conversely, when the output of the NAND gate 13 is equal to VDD, the output of the inverter 14 becomes 0V. Thereby, the transistor NM1 is turned on, and the gate of the transistor PM2 is put into 0V. In consequence, the transistor PM2 is turned on, and the gate of the transistor PM1 becomes VPX. At this time, the transistors NM2 and PM1 are turned off.
Thus, the first level shift circuit 15 converts the binary signal of [0V, VDD] as the output of the NAND gate 13 into the binary signal [0V, VPX].
On the other hand, a second level shift circuit 16 is composed of two pairs of transistors which are connected between a VPX node and a mode switching power supply voltage (VBB) in series. More specifically, the second level shift circuit 16 is composed of a transistor PM3 and a transistor NM3, and a transistor PM4 and a transistor NM4.
With this structure, the output is given to the gate of the transistor PM3 from a series connection point between the transistor PM2 and the transistor NM2. Further, the output is given to the gate of the transistor PM4 from a series connection point between the transistor PM1 and the transistor NM1.
Moreover, a series connection point between the transistor PM3 and the transistor NM3 is connected to the gate of the transistor NM4 while a series connection point between the transistor PM4 and the transistor NM4 is connected to the gate of the transistor NM3.
Subsequently, description will be made about an operation of a second level shift circuit 16.
When the output of the NAND gate is equal to 0V, the drain of the transistor NM2 is becomes 0V. Thereby, the transistor PM4 is tuned on to put the output signal XB into VPX. Consequently, the gate of the transistor NM3 becomes VPX, and the transistor NM3 is turned on to put the output signal XB into VBB. At this time, the transistors NM4 and PM3 are turned off.
Conversely, the output of the NAND gate 13 is equal to VDD, the drain of the transistor NM1 becomes 0 V. Thereby, the transistor PM3 is turned on to put the output signal XB into VPX. In Consequence, the gate of the transistor NM4 becomes VPX. As a result, the transistor NM4 is turned on to put the output signal XB into VBB. At this time, the transistors NM3 and PM4 are turned off.
Thus, the second level shift circuit 16 converts the binary signal of [0V, VPX] as the output of the first level shift circuit 15 into the binary signal of [VBB, VPX].
As mentioned before, the output signal XB is produced from the series connection point between the transistor PM3 and the transistor NM3 of the second level shift circuit 16 while the output signal XB is produced from the series connection point between the transistor PM4 and the transistor NM4. In this event, the output signals XB and XB are in the complementary relationship.
In this case, each voltage of each terminal in each operation mode of the row decoder illustrated in FIG. 1 is represented in FIG. 2.
Herein, it is assumed that the row main decoder MD illustrated in FIG. 1 is selected by the row address to select the word line WL1, and the word lines WL2-WLn and the row main decoders (not shown) are not selected.
With this example, description will be made about an operation of the row decoder MD, SD illustrated in FIG. 1.
In the writing operation, the mode switching power supply voltage VPX and the node switching power supply voltage VBB of the low potential side, which are applied to the row main decoder MD, are 5V and -9 V, respectively, as illustrated in FIG. 2. Further, the back gate voltage PBG of the p-channel transistor is equal to 0V while the back gate voltage NBG of the n-channel transistor is equal to -9 V.
When the output of the address decoder 13 becomes 0V, the output signal XB becomes a supply voltage 5V, and the output signal XB becomes -9 V. Further, the pre-decode signal XSPP1 is put into -9 V while XSPP2-n become 0V. Consequently, the transistor N11, and P21-Pn1 are turned on. As a result, the word line signal WL1 is put into -9 V while all of the word lines WL2-WLn are put into 0V.
In this event, the pre-decode signal XSPP1 of the memory block (not shown), which is not selected, becomes -9 V. However, the output signal XB becomes -9 V, and the output signal XB becomes the supply voltage 5V. Consequently, the transistors N12-Nn2 are turned on, and all of the word line signals WL1-WLn of non-selective blocks becomes 0V.
During the erasing operation, the mode switching power supply voltage VPX and the back gate voltage PBG is equal to 1 V, respectively. Further, the mode switching power supply voltage VBB at the low potential side and the back gate voltage NBG is equal to 0 V, respectively.
Moreover, the respective pre-decode signals XSPP1-n and the output signal XB are equal to 11 V, respectively while the output signal XB is equal to 0 V. As a result, the transistors P11-Pn1 are turned on, and the word line signals WN1-WLn are equal to 11V, respectively.
In this event, the pre-decode signals XSPP1-n of the non-selective memory blocks (not shown) are equal to 11V. However, the output of the address decoder 13 becomes VDD. Further, the output signal XB is put into 0V, and the output signal XB is put into 11V. Consequently, the transistors N12-Nn2 are turned on, and all of the word line signals WL1-WLn of the non-selective blocks becomes 0V.
During the reading operation, the mode switching power supply voltage VPX and the back gate voltage PBG become the power supply voltage, respectively. Further, the mode switching power supply voltage VBB at the lower potential side and the back gate voltage are equal to 0V, respectively.
When the output of the address decoder 13 becomes 0 V, the output signal XB becomes the supply voltage VDD and the output signal XB becomes 0 V. Further, the pre-decode signal XSPP1 is put into VDD while XSPP2-n are equal to 0 V, respectively. In consequence, the transistors P11, N21-Nn1 are turned on. Thereby, the word line signal WL1 is put into VDD while WL2-n are equal to 0V, respectively.
In this case, the pre-decode signal XSPP1 of the non-selective memory blocks (not shown) becomes VDD. However, the output of the address decoder 13 becomes VDD and the output signal XB is equal to 0V. Further, the output signal XB becomes the supply voltage VDD. Consequently, the transistors N12-Nn2 are turned on, and the word line signals WL1-WLn of the non-selective blocks become 0V, respectively.
Thus, the output signals XB, XB of the row main decoder MD for controlling the word line driving circuit SD becomes 5V at the high level and -9 V at the low level during the writing operation in the row decoder RD arranged for the flash memory. As a result, a high voltage of 5-(-9)=14V is applied to a PN junction of the transistor constituting the level shift circuit MD.
Namely, the back gate potential (NBG) of the transistor N12 constituting the word line driving circuit SD is put into -9V during the writing operation. Thereby, the threshold voltage becomes, for example, about 3.5 V because of the back gate bias effect.
To this end, it is necessary that the gate potential of the transistor N12 is selected to a higher value than 3.5 V to put the potential of the word line (WL) into 0 V by turning on the transistor N12.
Previously, no problem occurs because the supply power source VDD is used as VPX, and VDD is set to about 5V.
Recently, the supply power source VDD trends to become lower between 1.8 and 3.6V. When the semiconductor memory device is used with the low power supply voltage, the output voltage XB does not satisfy the threshold voltage of the transistor N12. Consequently, the transistor N12 is not turned on.
As illustrated in FIG. 3, a voltage of 14 V is applied between an N.sup.+ region and a P-well of a high voltage (a high breakdown voltage) of the transistor, and between a P.sup.+ region and a deep N-well. Consequently, it is necessary that the breakdown level of the PN junction is designed to (14+.alpha.)V. Herein, the deep well prevents the current from flowing across the junction portion when a negative potential is applied to a P-substrate (GND).
Therefore, it is necessary to form a diffusion layer having lower impurity concentration than a diffusion layer which forms source and drain of the transistor for supplying the supply voltage VDD, such as, the power supply voltage.
Consequently, two steps, namely, the formation step of the thin P-type diffusion layer and the formation step of the thin N-type diffusion layer additionally become necessary. This means that the number of the manufacturing steps and the manufacturing cost are increased.
In the meanwhile, disclosure has been made about a conventional non-volatile semiconductor memory for preventing a large electric field stress from being applied to a gate insulating film of a transistor in Japanese Unexamined Patent Publication No. Hei. 9-17189.
In such a non-volatile semiconductor memory (EEPROM), a row main decoder and a low sub-decoder are arranged in accordance with a plurality of cell-blocks.
In this case, the low sub-decoder includes a PMOS transistor which is inserted and connected between an input node of the cell-block and a word line, and an NMOS transistor for pull-down which is connected to the word line and a ground node.
On the other hand, the row main decoder produces a plurality of control signals of which potentials are restricted in accordance with during erasing selection/writing non-selection of the cell block and during erasing non-selection/writing selection, and supplies the respective control signals to the gate of the PMOS transistor and NMOS transistor of the row-sub decoder.
This EEPROM prevents the large electric filed from being applied to the gate insulating film of the specific transistor in the row sub-decoder during writing and erasing. In consequence, reduction of reliability can be avoided.
However, no consideration is taken about a negative voltage in the above-mentioned non-volatile semiconductor memory (EEPROM),
Further, the non-volatile semiconductor device is not applicable for the semiconductor memory device, such as, the flash memory. In semiconductor memory device, applied voltages to be applied to the memory cells during the writing operation are different from each other.